1. Field of the Invention
The present invention relates to built-in self-testing (BIST) for computer memories, and, in particular, to BIST testing for multiport memories.
2. Description of the Related Art
BIST testing refers to testing implemented by on-chip circuitry to verify the proper operation of a computer memory. BIST testing typically involves (1) writing known data into specific locations within a computer memory, (2) reading that data from those memory locations, and (3) comparing the read data with the expected (known) data to determine whether they are identical. If the read data does not match the expected data, then something in the computer memory architecture is not working properly. BIST testing can be designed to verify the proper operation of each memory cell in the computer memory, each write-address decoder used to write data into the computer memory, and each read-address decoder used to read data from the computer memory.
A wide variety of different types of computer memories are possible. In particular, different computer memories may have different numbers of bits per entry (i.e., bits per word or row), different numbers of entries, different numbers of write ports through which data can be written into the memories, and/or different numbers of read ports through which data can be read from the memories. In the past, BIST hardware and a corresponding BIST algorithm would be manually designed on a case-by-case basis for each different type of computer memory having a specific set of configuration characteristics (e.g., bits per entry, number of entries, number of write ports, and number of read ports).
A typical BIST hardware design relies on a different comparator for each different read port. That is, data read from the computer memory via a particular read port is forwarded to a corresponding comparator that processes data read from the memory via only that read port.